The present invention relates to the testing of a semiconductor memory device, more specifically to a method for testing for the presence and correct working of charge-replacing circuitry commonly found in semiconductor memory cells.
A large number of memory cells used in modern semiconductor memory arrays include pairs of transistors, cross-coupled to form bistable latches, as illustrated in FIG. 1. Such memory cells have two nodes, N1 and N2, represented by the drains of the respective transistors, hereafter referred to as storage transistors. By selectively coupling each node to a respective bit-line (xe2x80x9cbitxe2x80x9d, xe2x80x9cnotbitxe2x80x9d) and then taking one bit-line high and the other low, potentials can be stored on each of the nodes. More specifically, the first bit-line xe2x80x9cbitxe2x80x9d connected to the first node N1 may be taken high, thus taking the first node high, whilst the second bit-line xe2x80x9cnotbitxe2x80x9d, connected to the second node N2 is taken low, thus taking the second node low. It should be noted that for a bistable circuit to be in a stable state, the value stored on one node must be the logical opposite of that stored on the other node. An identical value on each node represents an unstable state and such instances only occur temporarily during certain reading or testing procedures, as described hereinbelow.
In the following description, the convention is adopted wherein the value stored by the cell is taken to be the value stored on the first node N1. For example, if the cell has a high (sometimes referred to as a xe2x80x981xe2x80x99) stored on the first node N1, and therefore a low (sometimes referred to as a xe2x80x980xe2x80x99) stored on the second node N2, the cell may be taken to be storing a high. Using the opposite convention the same cell would be deemed to be storing a low.
If the nodes are subsequently disconnected from the bit-lines, the bistable latch circuit would ideally retain its state indefinitely. However, charge from the node storing the high may leak through the respective storage transistor to ground. This may be caused by defects in the manufacturing process used to make the circuits or may be the unavoidable result of the way that the physics of manufacturing work. A common mode of leakage, other than a manufacturing defect, is charge leakage directly from the node to the ground terminal. This is due to the fact that the NMOS transistors commonly used in circuits of this type have sources and drains comprising N-type silicon which is fabricated in a P-type substrate. The NMOS sources and drains thus form P-N diodes with the substrate which are reverse biased during normal operation. These reverse biased diodes pass a small amount of current called xe2x80x9cleakage currentxe2x80x9d. Should this occur, the cell will retain its contents for a period of milliseconds or seconds but then lose its state. The faulty cell is then termed a weak bit.
To ensure that the contents of the cell will not be lost if the cell is left for a long period of time, circuitry for replacing any charge lost due to leakage is normally incorporated into the cell. Circuitry is connected between a positive voltage supply and each node of the memory cell. As charge leaks from the node, it is replaced by charge flowing through the charge-replacing circuitry (hereafter identified as CRC) from the positive voltage supply.
FIG. 1 shows a basic memory cell having no CRC. Because of charge leakage, such a cell will have no ability to retain its state for a long period of time once it is isolated from the bit-lines. The cell consists of four transistors, M1, M2, M4 and M6. M4 and M6 are the storage transistors and form the main body of the cell. Both have their sources connected to ground, and their gates and drains are cross coupled to form a bistable latch, with the drain of one connected to the gate of the other and vice versa. Nodes N1 and N2 are connected, respectively, to bit-lines xe2x80x9cbitxe2x80x9d and xe2x80x9cnotbitxe2x80x9d via access transistors M1 and M2. Transistors M1 and M2 have the function of coupling, respectively, nodes N1 and N2 to bit-lines xe2x80x9cbitxe2x80x9d and xe2x80x9cnotbitxe2x80x9d in response to an activating signal on word-line 10. When the activating signal on word-line 10 is low, access transistors M1 and M2 are turned off, isolating the cell from bit-lines xe2x80x9cbitxe2x80x9d and xe2x80x9cnotbitxe2x80x9d.
FIG. 2 shows a memory cell similar to that shown in FIG. 1, but which includes CRC for replacing charge lost due to leakage. This is a 6 transistor static RAM cell. In this diagram, the main body of the cell consists of four transistors, M3-M6. Transistor M4 has its drain connected to the gate of transistors M5 and M6 and to the drain of M3. Similarly, transistor M6 has its drain connected to the gate of transistors M3 and M4 and the drain of transistor M5. As before, nodes N1 and N2 corresponding, respectively, to the drains of transistors M4 and M6 are coupled to bit-lines xe2x80x9cbitxe2x80x9d and xe2x80x9cnotbitxe2x80x9d respectively via access transistors M1 and M2 which are activated in response to a signal on word-line 10. M3 and M4 form an inverter, as do M5 and M6. The inverters are cross-coupled so that the output of one inverter is the input of the other, forming a bistable latch. When the cell is isolated from the bit-lines xe2x80x9cbitxe2x80x9d and xe2x80x9cnotbitxe2x80x9d, by turning off M1 and M2, the main body of the cell will actively retain its state. Because the cell has active feedback through the inverters in the cell, any charge lost from N1 or N2 will be replaced by the CRC connected to that node.
FIG. 3 shows a similar cell to that shown in FIG. 2, but having CRC implemented as a high value resistance in series with the storage transistors. This is known as a 4 transistor static RAM cell. In the circuit shown in FIG. 3, the high value resistance takes the form of a pair of semiconductor diodes connected to each node. These diodes are connected in back-to-back arrangement, that is to say one diode is forward biased with respect to the voltage supply while the other is reverse biased with respect to the voltage supply. Thus the current passed by the diode pair is limited to the reverse saturation current of the reverse biased diode. This current is usually sufficient to replenish any charge lost due to leakage. However, the reverse biased diodes represent an effective resistance of tera-ohms to giga-ohms. Thus, the current passed by them is very small and if the charge leakage from the cell is relatively high, such a current may not be great enough to counteract the leaking charge. Furthermore, the circuit shown in FIG. 3 has the drawback that a pair of diode loads must be added to the cell, adding extra cost and complexity to the manufacturing process. Therefore, it is more common for the circuit of FIG. 2 to be used.
Often a cell is combined with many other cells to form an array comprising a plurality of columns of such cells and a plurality of rows of such cells. In an array, the cells in a column are connected via common bit-lines to allow reading and writing. The cells in a row are connected via common word-lines. The use of a cell with no CRC would cause the memory cells to fail unless a refresh circuit were coupled to counteract the effect of charge leakage every few milliseconds. This is not a practical solution. Incorporating CRC in one form or another thus provides a convenient way of ensuring that memory cells retain their state for a long period of time.
It is useful to be able to determine if the elements of the cell are functioning correctly. One test to achieve this is called the Marinescu 17N test and involves writing patterns of xe2x80x980xe2x80x99s and xe2x80x981xe2x80x99s into the cell and then reading them back and verifying them. The write part of the procedure is accomplished as outlined hereinabove, but the read part of the procedure is carried out as follows. The cell is isolated by turning off the word-line. The bit-lines are then charged to the supply voltage and the word-line is turned back on, reconnecting the bit-lines to the nodes. Charge will flow from the bit-line, through the node storing a low, through its respective storage transistor to ground. The potential on this bit-line will thus fall creating a potential difference between it and the other bit-line which will increase with time. This potential difference can be amplified by a sense amplifier and the contents of the cell can be verified. The potential on the other bit-line should not decrease with time since it is at the same potential as its respective node and thus no charge may flow through its respective access transistor. This procedure verifies the presence and correct working of the access transistors and the storage transistors, since if any are missing, the cell will be unable to store either a xe2x80x981xe2x80x99or a xe2x80x980xe2x80x99correctly. However, this test does not, by necessity, verify the presence and correct working of the CRC. It is important that this be done, since it is the CRC which ensures that the internal state of the cell is not lost if the cell is not accessed for a long period of time. It should be noted that if a cell with no CRC is accessed before the internal state is lost, the very act of connecting the nodes to the bit-lines in a read operation will refresh any state in the cell which has been degraded. If a cell with CRC is used, such as the cell shown in FIG. 2, and the CRC is compromised in some way, the cell reverts, either wholly, or in part, to the form of FIG. 1 and is known as a weak bit or, alternatively, as a cell with a data retention fault. There are two types of weak bit faults: symmetric faults, wherein the CRC on both sides of the cell fail, and asymmetric faults, wherein the CRC on only one side of the cell fails.
One test for the presence and correct functioning of the CRC is similar to the Marinescu 17N test described previously. A data pattern is written into the memory cells and then, after a long period of time, the data is read out and any discrepancies in the values of the cells are looked for. The inverse pattern is then written into the cells and the process is repeated. However, this test has a disadvantage in that a long period of time is needed to wait for any leakage effects to degrade the cell to the point where it loses its state. Since leakage is highly temperature and voltage dependent, this could take anything from between milliseconds to seconds. The total test time allocated to the testing of a typical semiconductor memory is normally approximately 2 to 3 milliseconds. The above test, however, may take several seconds to complete. Waiting for such a period of time to run only a data retention test far exceeds the budgeted test time by many orders of magnitude, thus slowing down production and increasing costs.
An alternative approach is to implement a test using a circuit called a controlled word-line driver (see Weak Write Test Mode: an SRAM Cell Stability Design for Test Technique, Anne Meixner and Jash Banik, 1996 International Test Conference Proceedings, IEEE Computer Society, IEEE Catalog No. 96CH35976, pp309-318). In this test, a voltage at an intermediate value between the ground potential and the supply potential is forced on to one of the nodes. This can be achieved by controlling the voltage level on the word-line. If the word-line is placed, for example, at half the voltage supply potential, then the voltage driven on to the node storing a high is the lower of the bit-line voltage or the voltage on the word-line minus the threshold voltage of the access transistor. When the word-line is turned off, the side of the cell storing a high will either remain at its current value because the CRC is missing or, if the CRC is working correctly, will be restored to the power supply voltage. Since the cell will have been sensitised so that it is closer to failing, the period of time needed to wait before data loss occurs is reduced. However, the implementation of such a test has disadvantages in that a separate power supply voltage is needed solely for the circuit which drives the word-line (the word-line driver). It also requires careful characterisation to determine what the best value of the word-line voltage should be to make the test successful. Also, an indeterminate period of time is still needed for leakage to occur.
It would be advantageous to have a method for testing for the presence and correct working of the CRC which does not require circuitry to be added to the cell other than that shown in FIGS. 2 or 3, and which can be carried out in a greatly reduced period of time. The present invention is aimed at addressing this problem.
According to one aspect of the present invention, therefore, there is provided a method for testing a semiconductor memory cell comprising first and second transistors in cross-coupled arrangement to form a bistable latch, the drains of the transistors respectively representing first and second nodes each for storing a high or low potential state, and each node being connected to a respective semiconductor arrangement for replacing charge leaked from the node and to a respective switching means, activatable by a word-line, for coupling the node to a respective bit-line, the method comprising the steps of: connecting the bit-lines to the low potential; activating the word-line to connect the first node to the first bit-line to allow any potential on the first node to fall towards the potential on the first bit-line; and monitoring charge flow from the first node to the first bit-line to test the operation of the first semiconductor arrangement.
Furthermore, according to another aspect of the present invention, there is provided apparatus for testing a semiconductor memory cell comprising first and second transistors in cross-coupled arrangement to form a bistable latch, the drains of the transistors respectively representing first and second nodes each for storing a high or low potential state, and each node being connected to a respective semiconductor arrangement for replacing charge leaked from the node and to a respective switching means, activatable by a word-line, for coupling the node to a respective bit-line, the apparatus comprising: switching circuitry for connecting both bit-lines to the low potential; and testing circuitry connected to the first bit-line for monitoring charge flow from the first node to the first bit-line.
Preferably, the first semiconductor arrangement is deemed to be functioning if the flow of current from the first node to the first bit-line reaches a predetermined level or if the potential of the first bit-line reaches a predetermined level within a predetermined period of time.
Preferably, the first semiconductor arrangement is deemed not to be functioning if the flow of current from the first node to the first bit-line does not reach a predetermined level or if the potential of the first bit-line does not reach a predetermined level within a predetermined period of time.
The predetermined period of time is suitably in the range from 10 to 100 ns, preferably in the range from 30 to 70 ns and most preferably around 50 ns from connection of the bit line to the node.
Preferably, the first semiconductor arrangement comprises a PMOS transistor.
Alternatively, the first semiconductor arrangement may comprise a pair of diodes.
Preferably the switching means comprises one or more transistors.
The testing circuitry may comprise a threshold circuit.
Preferably, the potential of the first bit-line is measured by a threshold circuit.
The threshold circuit may be provided by an inverter.
The threshold circuit may be set to switch when the potential of the bit line rises to between 10% and 80% of the said higher potential, preferably between 30% and 60%, most preferably around 50%. The potential at which the threshold circuit is set to switch may be at the threshold for a high logic level in the system, or may be lower than that threshold. The testing circuitry may comprise an amplifier for amplifying charge flow from a bit line.
Preferably, the switching circuitry for connecting the bit-lines to a low potential comprises a plurality of logic gates and/or a plurality of transistors.
The memory cell is preferably a 6 transistor static RAM cell.
Alternatively, the cell may be a 4 transistor static RAM cell.
The cell is preferably formed on an integrated circuit. The integrated circuit preferably comprises a plurality of cells, suitably connected in an array by common bit and word lines.
The integrated circuit preferably also comprises the testing circuitry and/or means for connecting both bit lines of the cell to a low potential at the same time.
A method according to the invention may also comprise testing the first semiconductor arrangement as described above and then, in an analogous way testing the second semiconductor arrangement.
Where the cell is one of several on an integrated circuit the method may comprise testing semiconductor arrangements of all those cells. More than one cell of such a circuit may be tested simultaneously. It is envisaged that 32, 64 or 128 cells may be tested simultaneously in parallel.